#include "config.h"
#include "m14kc.h"
        .section 	.start,  "ax"
        .globl  	_start
        .ent    	_start
_start:
        .set		noreorder
        .set    	noat            	# Don't allow the assembler to use r1(at) for synthetic instr.
        b       	reset_nmi       	#1f
        nop
        nop                      		/* 0xBfc00008 */
        nop                       		/* 0xBfc0000C */
        .word   	0xffffffff      	/* 0xBfc00010 - illegal board if not intercepted */
        .word   	0xffffffff      	/* 0xBfc00014 - expanded to 64 bit */
        .set		at
        .set   	 	reorder			# Linker ok to reorder
        .end  	 	_start          	# Linker end of function

        .text
reset_nmi:
        .set 		noreorder 	# Linker don't change instruction order
        .set 		noat
        # Disable Coprocessor Usable b[31:28] = CU3-0
        # Turn off Reduce Power b[27] = RP
        # Turn off Reverse Endian b[25] = RE
        # Turn off BEV (use normal exception vectors) b[22]
        # Clear TS, SR, NMI bits b[21:19]
        # Clear Interrupt masks b[15:8] = IM7-0, IM8-9 disabled
        # Clear User Mode  b[4:3] = Kernel mode
        # Clear ERL b[2]
        # Set EXL b[1] (in kernel mode, and interrupts diabled)
        # Clear Interrupt Enable b[0]
        li      	t3, 0x00000002
        mtc0    	t3, CP0_STATUS

        /* Set shadow register set for 1 of the all Vector interrupts. 	*/
        /* interrupt 0-7 will use register set 1. The last set is current */
        li      	t1, 0x11111111  	# each field is 4 bits
        mtc0    	t1, CP0_SRSMAP
        ehb                     		# Wait for change to take effect

        /* Now set the interrupt in the stack pointer of the shadow */
        /* register set #1, CSS is 0 on reset */
        li      	t1, 0x04001040	# ESS with 1 GPR, PSS&CSS with the same 0 GPR
        mtc0    	t1, CP0_SRSCTL   # Write it back
        ehb

#if defined(CONFIG_MMU) && (CONFIG_MMU>0)
#include "arch/T1/mmu.h"
#define PADDR0		0x10000000	// mapped elfash(total 192KB)
#define VADDR0		0x70000000	// to
#define PSIZE0		PSIZE_256K	// means 512KB mapped
#define TLB_ID0		0
#define LO_CDVG0	(C_TYPE3 | V_EN | G_EN)
	mmu_map VADDR0, PADDR0, PSIZE0, TLB_ID0, LO_CDVG0
#define PADDR1		0x00000000	// mapped sram(total 64KB)
#define VADDR1		0x60000000	// to
#define PSIZE1		PSIZE_64K	// means 128KB mapped
#define TLB_ID1		1
#define LO_CDVG1	(C_TYPE3 | V_EN | G_EN | D_EN)
	mmu_map VADDR1, PADDR1, PSIZE1, TLB_ID1, LO_CDVG1
#endif
		/* config EBase */
        la			t1, _ebase
        #li	        t1, 0x90000000
        mtc0		t1, CP0_EBASE
        ehb
        /* Set up boot stack and interrupt stack. */
        la      	sp, _sp
        la      	gp, _gp
        la      	t1, _sp_it
        wrpgpr  	sp, t1
        wrpgpr  	gp, gp

        /* move data section to run time area and clear bss section.*/
        /* enable D-Cache and I-Cache */
        bal 	    data_section_init
        nop
 
        bal         cache_init
        nop
        bal         en_cache
        nop
 
        /* init config3 ISAOnExc,
           microMIPS is used on entrance to an exception vector */
        mfc0	 	t2, CP0_CONFIG3
        li			t3, 0x10000
        or			t2, t2, t3
        mtc0	 	t2, CP0_CONFIG3

        /* clear cause, enable CP0 Count */
        mtc0	 	zero, CP0_CAUSE
	mtc0		zero, CP0_COMPARE	# Write to clear TI flags in Cause
        ehb

        /* Set Status register (C0_STATUS) */
        /* This will enable interrupts IM2 */
        li 			t0, 0x00000401
        mtc0		t0, CP0_STATUS		# Write the status register
        ehb 				        	# Wait for change to take effect

		syscall

        //jal      	start_kernel
        la		ra, start_kernel
        jr		ra
        nop
        .set	  	at
        .set    	reorder
